1. Field of the Invention
The present invention generally relates to high bandwidth/performance Dynamic Random Access Memories (DRAMs) and, more particularly, to high bandwidth/performance DRAMs with improved, lower page-hit latency.
2. Description of the Related Art
Dynamic random access memory (DRAM) performance is a well known limitation to computer system performance. Processor speeds are rapidly outpacing main memory performance, with both processor designers and system manufacturers developing higher performance memory subsystems in an effort to minimize performance limitations due to the slower DRAM devices. Ideally, the memory performance would match or exceed processor performance, i.e., a memory cycle time would be less than one processor clock cycle. This is almost never the case and, so, the memory is a system bottleneck. For example, a state of the art high speed microprocessor may be based on a 200 MegaHertz (MHZ) clock with a 5 nanosecond (ns) clock period. A high performance DRAM may have a 60 ns access time, which falls far short of processor performance.
This system bottleneck is exacerbated by the rise in popularity of multimedia applications. Multimedia applications demand several times more bandwidth for main memory or frame-buffer memory than computational intensive tasks such as spread sheet analysis programs or, other input/output (I/O) intensive applications such as word processing or printing.
Extended Data Out (EDO) and Synchronous DRAMs (SDRAMs) were developed to improve bandwidth. However, SDRAMs and EDO RAMs still do not match processor performance and, therefore, still limit system performance. Consequently, as faster microprocessors are developed for multimedia processing and high performance systems, faster memory architecture is being developed to bridge the memory/processor performance gap, e.g., wide I/O DRAMs.
Recent developments predict a major turning point for memory devices and related subsystems with a shift to high speed/narrow I/O devices. Although these new devices offer a significant increase in burst speeds, they do not offer improvements in latency for initial accesses. That is, for an initial access or page hit, it typically takes a number of clock cycles before the data read out from the DRAM appears at the DRAM chip pins.
Thus, there is a need for high bandwidth DRAM chips that have a decreased page-hit latency.